Multitasking processor system for monitoring interrupt events

ABSTRACT

In a processor system, different memory means ( 8 ), which can in each case comprise a memory stack ( 9 ) for the instruction counter, a register ( 10 ) for temporarily storing data and status register ( 11 ), are provided for various tasks. When an interrupt event (EV) occurs which causes a change from a current task to a new task, a controller ( 21 ) switches from the memory means ( 8 ) allocated to the old task to the memory means ( 8 ) allocated to the new task.

DESCRIPTION

1. Technical Field

The present invention relates to a processor system according to theprecharecterizing clause of claim 1, which is pro interrupts.

2. Background Art

Telecommunication terminals such as, for example, modems or so-calledline cards must be able to respond to particular software or hardwareevents. If a processor system is used for control purposes in suchtelecommunication terminals, interrupt processing is usually provided inthe processor system so that it can respond to the events describedabove.

For the interrupt processing, the individual events which can trigger aninterrupt in the processor system are monitored. As soon as theoccurrence of an interrupt event has been detected, a correspondinginterrupt request signal is generated and transmitted to a processorunit of the processor system which thereupon determines the startaddress of the corresponding interrupt routine which is supposed to runfor executing the interrupt in the processor system. If a number ofinterrupt events occur at the same time, only one particular interruptevent of these interrupt events is selected in accordance with apredetermined scheme for executing the corresponding interrupt. Thevalue of the program counter (PC) of the task running before theinterrupt in the processor system is saved in a memory stack so that theinterrupt routine can be subsequently executed. After the interruptroutine has ended, the original task can be continued again by accessingthe saved program counter.

Before the interrupt routine is performed, it is generally not only theinstantaneous value of tire program counter but also other informationon the status of the processor system and, respectively, of the taskrunning on it which have to be saved before the interrupt event occurs.This status information can relate, in particular, to the contents ofregisters or zero and carry flags etc. In known processor systems,therefore, so-called shadow registers are used for accelerating theinterrupt processing which represent additional registers which onlymake an appearance in the case of an interrupt for saving the abovestatus information and are not used otherwise (compare, e.g. “ARM SystemArchitecture”, Steve Furber, Addison-Wesley, 1996). This makes itpossible to avoid having to use time-consuming register storage commandsfor saving the information described.

However, the abovementioned approach only represents an effectivemeasure if it is intended to run only one task in the processor system.In so-called multitasking processor systems in which a number of taskscan run simultaneously or virtually simultaneously, this approach cannotbe easily used since different program counters must be taken intoconsideration for the individual tasks in this case. In addition, theapproach described above is relatively expensive due to the use of theadditional shadow registers.

SUMMARY OF THE INVENTION

The present invention is, therefore, based on the object of proposing aprocessor system with interrupt processing in which a change of thetask, caused by a corresponding interrupt, can be performed with lessexpenditure.

According to the invention, this object is achieved by a processorsystem having the features of claim 1. The subclaims define advantageousand preferred embodiments of the present invention.

According to the invention, different storage means are provided fordifferent tasks and the storage means can comprise, in particular, amemory for the program counter of the respective task, registers fortemporarily storing data during the execution of the respective task andstatus registers for storing status information such as, for example,carry or zero flags. If it is intended to switch from one task toanother task on occurrence of a particular interrupt event, it is onlynecessary to switch to the storage means allocated to the new task forthis purpose. The provision of separate hardware areas for differenttasks thus provides for a hardware-supported multitasking operation ofthe processor system without having to perform a multiplicity of savingprocesses when switching to a new task.

The different interrupts are preferably processed under prioritycontrol, individual priorities being assigned both to the correspondinginterrupt events and to the tasks running in the processor system. Aparticular priority level is preferably defined which can lead to achange of task. It is only events having this particular priority levelwhich can cause a change of task. The consequence of any other events isonly that a start address is generated for the corresponding interruptroutine.

The present invention is suitable, for example, for being used intelecommunication terminals such as, e.g. modems or line cards andapplies, in particular, to xDSL terminals.

BRIEF DESCRIPTION OF THE DRAWINGS

In the text which follows, the invention will be explained by means of apreferred illustrative example and referring to the attached drawing, inwhich:

FIG. 1 shows a simplified block diagram of a processor system accordingto a preferred illustrative embodiment of the present invention,

FIG. 2 shows a possible implementation of a program control unit shownin FIG. 1,

FIG. 3 shows a possible implementation of an event evaluating unit shownin FIG. 2, and

FIG. 4 shows a possible implementation of a monitoring unit shown inFIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

The processor system shown in FIG. 1 comprises a processor unit 1 whichcomprises, among other things, a program controller 12 and aninstruction decoder 5, a so-called branch control unit (BCU) 6 and atleast one arithmetic logic unit (ALU) 7. In addition, an individual ortask-specific hardware environment 8 is provided for each task which canbe executed on the processor system and which in each case comprises amemory stack 9, a register bank with one or more registers 10 and one ormore status registers 11. In the memory stack 9, the instantaneous valueof the program counter (PC) of the corresponding task is stored in eachcase. The registers 10 are used for temporarily storing data during theprocessing of the corresponding task. The status registers 11, on theother hand, are intended for storing status information or status flagssuch as, for example, zero or carry flags so that the content of thestatus registers in each case designates the current status of thecorresponding task.

The program controller 12 monitors a number of interrupt events EV. Whena particular interrupt event occurs, either a corresponding interruptroutine is started or a change of task is performed. The programcontroller 12 thus specifies the current task in each case and theinstruction to be executed within this task, and thus the valve of theprogram counter of this task and outputs corresponding information.

Using this value of the program counter PC, output by the programcontroller 12, it is possible to access a program memory 2 and read outa corresponding instruction INST. This instruction INST is decoded bythe instruction decoder 5 and supplied to the BCU 6 and the ALU 7 forexecution and these two lastmentioned units also know the number of thetask to be processed. Together with the instruction decoder 5, the BCU 6ensures that the correct hardware environment 8, i.e. the hardwareenvironment actually provided for the task to be processed, is alwaysaccessed. The BCU 6 is responsible for hardware switching between thememory stacks 9 which are provided for the individual program countersPC whereas the registers 10 and the status registers 11 are accessedboth by means of hardware switching by the BCU 6 and in software bymeans of an internal instruction by the instruction decoder 5. The ALU7, finally, executes the instruction INST by using the correspondinghardware environment 8, and it may be necessary to address a data memory3 for this purpose in which an address signal ADR is stored and it isestablished with the aid of a control signal R/W whether the data DATAare to be read out of the data memory 3 or to be written into the datamemory 3. Similarly, it may be necessary, as a consequence of theexecution of the instruction, to address one or more input/output ports4 to which an address signal ADR is to be applied in order to be able toread data DATA from an output port 4 or to write data DATA into an inputport 4.

FIG. 2 shows a possible implementation of the program controller 12. Anevaluating unit 13 monitors the occurrence of the individual interruptevents EV and generates in dependence on these an interrupt requestsignal IRQ with a start address VEC for the corresponding interruptroutine or a switching signal SWITCH for initiating a change of taskwith information TASK on the task to which it is intended to switch. Acontrol unit 21 receives this information from the evaluating unit 13and initiates in dependence thereon, as already described, the use ofthe correct hardware environment 8 in each case. For this purpose, thecontrol unit 21 outputs, on the one hand, an information item CTASK onthe task currently to be executed to the instruction decoder 5 and theBCU 6 and the program counter PC corresponding to this task CTASK foraddressing the program memory z.

Interrupt processing takes place under priority control. For thispurpose, an individual priority is assigned to each task and to eachinterrupt event EV. The priority PRIO of the current task is reported tothe evaluating unit 13 by the control unit 21. In principle, a task canonly be interrupted by an interrupt if the corresponding interrupt eventhas a higher priority than the task. Accordingly, the priority of a taskmust be decremented by the task itself or by another task if it is to bepossible to interrupt the corresponding task also by interrupt eventshaving a lower priority level. A task having the highest priority levelcan only be interrupted by interrupt events which also have the highestpriority level. This can apply, for example, to a reset interrupt.

Within the various priority levels, a particular priority level isdefined which exclusively leads to a change of task. i.e., it is onlyinterrupt events having this priority level which can cause a changebetween the individual tasks so that the information SWITCH and TASKshown in FIG. 2 is only generated and supplied to the control unit 21when these interrupt events occur. Any other interrupt events only leadto the interrupt request IRQ being output by the evaluating unit 13 witha vector VEC which contains the branch or start address for theinterrupt routine to be executed. The control unit 21 is thus suppliedeither with the SWITCH and TASK signals or the IRQ and VEC signals. Inthe former case, a corresponding interrupt routine is called up whereas,in the latter case, a change of task takes place. The IRQ signal and theSWITCH signal cannot occur at the same time.

FIG. 3 shows a possible implementation of the evaluating unit 13 shownin FIG. 2 and it is assumed that three different priorities are definedand priority “2” is the priority provided exclusively for a change oftask. For each group of interrupt events EV_1 . . . EV_3 which have thesame priority, a separate monitoring unit 14_1 . . . 14_3 is providedwhich exclusively monitors the occurrence of the interrupt eventsassigned to it and the priority PRIO of the task currently processed.

As soon as the monitoring unit 14_1 or 14_3 has detected the occurrenceof an interrupt event EV_1 or EV_3 allocated to it, an interrupt requestsignal IRQ is generated and a downstream unit 15_1 or 15_3,respectively, generates in dependence on the interrupt event which hasoccurred a corresponding vector VEC which designates the required startaddress for the interrupt routine to be executed. The signal thusgenerated are supplied to multiplexers 16 or 17, respectively, themultiplexers 16 and 17 being switched in dependence on the prioritycontrol signal PRIO and switching in dependence thereon only one of thetwo input signals through to their output and supplying it to thecontrol unit 21 shown in FIG. 2.

The monitoring unit 14_2 is provided exclusively for monitoring theinterrupt events EV_2 which have priority “2” and can thus cause achange of task by definition. As soon as the monitoring unit 14_2 hasdetected the occurrence of an interrupt event EV_2 allocated to it, theswitching signal SWITCH is generated which instructs the control unit 21to perform a change of task and a downstream unit 15_2 generates independence on the interrupt event which has occurred, in the form of theinformation item TASK, the number of the task to which it is intended toswitch.

Within each monitoring unit 14_1 . . . 14_3, subpriorities can bedefined if the corresponding monitoring unit always scans its inputswith regard to the occurrence of the corresponding interrupt event inthe same order, for example always from top to bottom.

FIG. 4 shows a possible implementation of the monitoring unit 14_1 shownin FIG. 3, and the downstream unit 15_1.

The monitoring unit 14_1 comprises an input memory 19 in which acorresponding bit is set when one of the interrupt events EV_1 occurs. Abit monitoring unit 20 monitors the individual bits of the input memory19 in correspondence with a predetermined clock CLK. As soon as the bitmonitoring unit 20 has detected a set bit in the input memory 19, theinterrupt request signal IRQ is generated and, depending on the positionof the bit set in the input memory 19, the vector VEC with the start orbranch address for the required interrupt routine is generated. For thispurpose, the position of the bit set in the input memory 19 is mapped tothe corresponding start address by the unit 15_1, this being done, asshown in FIG. 4, by first performing a bit shift operation by n bits(corresponding to a multiplication via the factor 2^(n)) and then anaddition with a particular offset value OFF. After that, the bit set inthe input memory 19 is cleared again with the aid of a clear signalCLEAR.

The bit monitoring unit 20 is also used for monitoring the priority PRIOof the current task. Generation of the interrupt request signal IRQ andof the vector VEC with the start address of the corresponding interruptroutine is only enabled by the bit monitoring unit 20 if the priorityPRIO of the current task is less than the priority of the correspondinginterrupt event.

FIG. 4 also shows the possibility that individual interrupt events canbe masked, i.e. made invisible for the bit monitoring unit 20, with theaid of a masking circuit 18.

In the present example, this masking circuit 18 is designed in the formof AND gates which can be programmed with the aid of a correspondingsignal MASK. Such an individually programmable masking circuit 18 ispreferably used before each monitoring unit 14_1 . . . 14_3.

The monitoring unit 14_3 and the corresponding unit 15_3 can beconfigured identically to FIG. 4. Similarly, the monitoring unit 14_2can be configured identically to FIG. 4. The configuration of the unit15_2, on the other hand, differs from FIG. 4 in that the unit 15_2 doesnot map the position of a bit set in the corresponding input memory 19to an address but to a task number.

1. A multitasking processor system comprising: a program controllerwhich has an evaluating unit for monitoring an occurrence of interruptevents and a control unit which is provided for controlling an executionof an interrupt routine when the evaluating unit detects the occurrenceof said interrupt events, said processor system further comprisingdifferent memory circuits which are provided for different tasks in themultitasking processor system, wherein the control unit is designed insuch a manner that, on the occurrence of interrupt events which causes achange from a current task to a new task and which have a particularpredetermined priority level, the control unit initiates, for executingthe new task, a switchover from a memory circuit allocated to thecurrent task to a memory circuit allocated to the new task, wherein thememory circuit exhibiting in each case one memory for a program counterof an associated task, at least one register for temporarily storingdata which are produced during execution of the associated task, and atleast one status register for storing status information of theassociated task, wherein individual priorities are allocated to theindividual interrupt events and at least one particular priority isprovided for change to a new task, and wherein the evaluating unit, ondetection of the occurrence of interrupt events having the particularpredetermined priority forwards a corresponding request for a changefrom the current task to the corresponding new task to the control unit.2. The processor system as claimed in claim 1, wherein individualpriorities are allocated to the individual tasks which can be executedby the processor system, wherein said individual priorities areallocated to the individual interrupt events, and wherein the evaluatingunit is designed in such a manner that, on detection of the occurrenceof an interrupt event, the evaluating unit only forwards a correspondingrequest for execution of the corresponding interrupt to the control unitif the priority of the corresponding interrupt events is higher than thepriority of the task currently executed in the processor system.
 3. Theprocessor system as claimed in claim 2, wherein the evaluating unit isdesigned in such a manner that, on detection of the occurrence of aninterrupt event having the particular priority together with the requestfor the change from the current task to the corresponding new task, theevaluating unit also forwards an information item specifying the newtask to the control unit.
 4. The processor system as claimed in claim 2,wherein the evaluating unit is designed in such a manner that, when theoccurrence of an interrupt event is detected, the evaluating unit onlyforwards a corresponding request for execution of the correspondinginterrupt together with an address specifying a corresponding interruptroutine to the control unit if the priority of the correspondinginterrupt events is higher than the priority of the task currentlyexecuted in the processor system and the priority of the interruptevents does not correspond to the particular priority.
 5. The processorsystem as claimed in claim 1, wherein the evaluating unit comprises aseparate monitoring device for each possible priority of the interruptevents, each monitoring device monitoring the occurrence of theinterrupt events having the corresponding priority in each case.
 6. Theprocessor system as claimed in claim 5, wherein the evaluating unitcomprises for each monitoring device a separate masking circuit whichprecedes this monitoring device.
 7. The processor system as claimed inclaim 1, wherein the evaluating unit is preceded by a programmablemasking circuit which masks the occurrence of corresponding interruptevents for the evaluating unit in dependence on its programming.
 8. Theprocessor system as claimed in claim 1 wherein, the processor system isused in a telecommunication terminal, particularly in an xDSLtelecommunication terminal.